PICMG 2.16 Overview Tutorial

PICMG® 2.16 Tutorial - continued

Limitations of the PCI Bus

CompactPCI® has some inherent shortcomings that had to be addressed for next-generation applications.

First, the PCI bus is a shared bus architecture with a theoretical throughput limitation of 533MB/sec over only five slots. This performance is far below even moderate Ethernet capabilities.

Also, drivers compatible with the operating system (OS) installed in the slot-one controller must be in each chassis unit. Although many capable CompactPCI subsystems are available, vendor selection and system capabilities generally are limited when developing a product based on a preferred OS. And the lack of an appropriate driver for a component will delay development pending completion and debugging of the OS-specific driver.

Meantime, standard CompactPCI subsystems have only a single CompactPCI bus interface, so the entire system becomes inoperable if the interface controller on one subsystem seizes the bus, meaning a single point of failure can stop a system. While a level of resilience can be provided (at a higher cost) by redundant CompactPCI buses on the same mid-plane, chassis-width and speed limits imposed by CompactPCI remain unavoidable obstacles.

Time-to-Market

Another major factor in developing the PICMG 2.16 spec was the need to reduce integration time. With time-to-market so critical in today's fast-paced, high-tech industry, something had to be done. In a 2.16 system, development occurs at the Network/Transport level, NOT at the Link (driver/backplane) level. This drastically reduces integration time - while increasing system scalability, reliability and performance.

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